1. Field of the Invention
The present invention relates generally to microelectronic or semiconductor circuits and, more particularly, to structures, materials, and methods used to form graded layers that may be used, for example, in a gate stack for a transistor or to form the conductive lines used for interconnecting circuit elements within a microelectronic circuit.
2. Background of the Related Art
Many devices today contain microelectronic or semiconductor circuits. These circuits usually contain a number of circuit elements that perform the desired function of the semiconductor circuit. Semiconductor circuits, such as memories, typically contain thousands of interconnected transistors. Transistors are usually three terminal devices that may take many forms. One type of transistor is known as a field effect transistor (FET). The terminals of a FET are known as a gate, a source, and a drain. Formation of a FET""s source and drain regions within a semiconductor""s substrate is usually achieved by doping selected regions of the substrate. Formation of a FET""s gate is usually achieved by depositing or growing a dielectric oxide layer on top of the substrate between the doped source and drain regions and by depositing a conductive material on top of the gate oxide.
Other layers may be added to the gate region of a FET. The combination of the layers formed over the gate region are referred to collectively as the transistor gate stack. For instance, layers may be formed to interconnect the FET with other portions of the circuit. One interconnecting layer may be formed of semiconductive or conductive material, such as polysilicon, that is deposited on top of the gate oxide. Another interconnecting layer may be formed of conductive material, often a silicide material such as tungsten silicide (WSix) or titanium silicide (TiSi2), that is deposited on top of the first interconnecting layer. Insulating or barrier layers may also be formed within the gate stack for various reasons.
As the density of semiconductor devices has increased, the dimensions of the features and layers on the semiconductive wafer have become smaller. For instance, the length and width of transistor gates has been reduced, as has the height of the gate stack due to the thinner layers used therein. The various material layers that form an integrated circuit typically are subjected to stress due to differences in their structural properties, and this stress becomes important as the thickness of the various layers increases. More specifically, this stress is caused by differing residual stress levels in adjacent material layers, resulting in part from the thermal expansion properties of adjacent layers. This stress can cause the peeling or separation of one layer from adjacent layers. This peeling or separation is further exacerbated as the silicon wafer size increases. Additionally, wafer warpage tends to increase with wafer size, which further affects the stress in the layers. Thus, as semiconductor device geometries shrink, a need for better adhesion and lower stress between layers, such as the gate dielectric layer and the gate conductive layer, is desirable.
High stress that can lead to peeling or delamination may cause the resistance of the delaminated layers to increase and result in problems, such as increased RC time constants. Therefore, there also exists a need for a gate stack that has a reduced resistivity as compared with previously used gate stacks and that would be suitable for use in very small device geometries, such as those in the sub 0.15 micron range.
Additionally, conductive layers, such as those formed from silicide, may not maintain the desired levels of resistivity and thermal stability over a desired temperature range. For example, there is the need for a barrier layer to maintain these properties when exposed to temperatures exceeding 700xc2x0 C. during processing steps subsequent to formation of the conductive layer.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In accordance with one aspect of the present invention, there is provided a transistor gate stack. The transistor gate stack includes a dielectric layer that is disposed on a substrate. A gate layer is disposed on the dielectric layer. A graded layer is disposed on the gate layer. The graded layer has a first region of a first material and a second region of a second material.
In accordance with another aspect of the present invention, there is provided a layer for use in fabricating an interconnect. A graded layer is disposed between a first material and a second material. The graded layer has a changing material composition from a first region proximate the first material to a second region proximate the second material.
In accordance with a further aspect of the present invention, there is provided a method of forming a transistor gate stack structure. The method includes the steps of forming a dielectric layer on a substrate, forming a gate layer on the dielectric layer, and forming a graded layer on the gate layer, where the graded layer has a first material in a first region and a second material in a second region.
In accordance with yet another aspect of the present invention, there is provided a method of forming a layer for use in fabricating an interconnect. The method includes the step of forming a graded layer between a first material and a second material. The graded material has a changing material composition from a first region proximate the first material to a second region proximate the second material.
In accordance with still another aspect of the present invention, there is provided a transistor gate stack A dielectric layer is disposed on a substrate A gate layer is disposed on the dielectric layer. A graded layer is disposed on the gate layer The graded layer is formed by varying the material composition of the graded layer during deposition of materials forming the graded layer.